PL8322 30V, 3.1A Monolithic Buck Converter with CC/CV Control 1 Features 2 Applications  3.1A continuous output current capability  Car charger  6.5V to 30V wide operating input range with input  Portable charging device  General purpose USB charger Over Voltage Protection  General purpose DC-DC conversion  Integrated 36V, 76mΩ high side and 36V, 52mΩ low 3 Description side power MOSFET switches  Up to 95% efficiency PL8322 integrates a high efficiency synchronous  CV/CC Mode control (Constant voltage and step-down switching regulator, which includes a 36V, 76mΩ high side and a 36V, 52mΩ low side constant current). Cycle-by-Cycle Current Limiting MOSFETs to provide 3.1A continuous load current  Configurable Line Drop Compensation with resistor over 6.5V to 30V wide operating input voltage with  Configurable Charging Current Limit with resistor 33V input over voltage protection. Peak current mode  Internal Soft-Start limits the inrush current at turn-on control provides fast transient responses and  Internal compensation to save external components cycle-by-cycle current limiting. PL8322 has  Stable with Low ESR Ceramic Output Capacitors configurable line drop compensation, configurable  Fixed 100KHz Switching Frequency charging current limit. CC/CV mode control provides  Input Under-Voltage Lockout. Output Over-Voltage a smooth transition between constant current charging and constant voltage charging stages. Protection Built-in soft-start prevents inrush current at power-up.  Over-Temperature Protection  Soft start time is programmable using external capacitor  33V input voltage protection to protect power MOSFETs from working at high current ,high input voltage condition  Thermally Enhanced ESOP-8 Package 4 Typical Application Schematic \& Efficiency VIN/6.5V-30V 2 1 C5 L1 Vout/5V VIN BST 100nF/25V 22uH 3 R1 SW 31.6k C1 C2 5 1% C4 C3 100uF/50V 0.1uF/50V FB 0.1uF 100uF R2 EN 7 EN PL8322 10k 1% C6 47pF 8 SS IADJ 6 C7 GND R3 100nF/25V 4 ADJ * C6 is optional. Fig. 1 Schematic Fig. 2 Efficiency curve DS-PL8322-Rev. 1.0 1of 315 2016-03-20 © Powlicon Inc.

PL8322 5 Pin Configuration and Functions ESOP-8 Package (Top View) BST 1 PL8322 8 SS VIN 2 7 EN SW 3 EXPOSED 6 IADJ GND 4 PAD FB 5 Pin Pin-Functions Number Name Description 1 BST Boot-Strap pin. Connect a 0.1µF or greater capacitor between SW and BST to power the 2 VIN high side gate driver. Power Input. Vin supplies the power to the IC. Supply Vin with a 6.5V to 30V power source. 3 SW Bypass Vin to GND with a large capacitor and at least another 0.1uF ceramic capacitor to 4 GND eliminate noise on the input to the IC. Put the capacitors close to Vin and GND pins. Power Switching pin. Connect this pin to the switching node of inductor. 5 FB Ground. Feedback Input. FB senses the output voltage. Connect FB with a resistor divider connected 6 IADJ between the output and ground. FB is a sensitive node. Keep FB away from SW and BST 7 EN pin. It is better to connect a 47pF ceramic capacitor between FB pin and GND pin. 8 SS Connect a resistor between IADJ and GND to configure load current limit and line drop compensation. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator; low to turn it off. EN pin is pulled to VIN internally by a larger resistor. This pin is used to program soft-start time, connect a cap to program soft-start time. 6 Device Marking Information Part Number Order Information Package Package Qty Top Marking PL8322 PL8322IES08 ESOP-8 2500 8322 RAABB PL8322: Part Number RAABB: Lot Number. R: Year; AABB: Manufacturing Code 7 Specifications 7.1 Absolute Maximum Ratings(Note1) PARAMETER MIN MAX Unit V Input Voltages VIN to GND -0.3 36 V Output Voltages VSS to GND -0.3 6 VEN to GND -0.3 6 VFB to GND -0.3 6 VIADJ to GND -0.3 6 VBST to VSW -0.3 6 VSW to GND -1 VIN+ 0.3 DS-PL8322-Rev. 1.0 www.powlicon.com 2 of 16 2016-03-20 © Powlicon Inc.

7.2 Handling Ratings PL8322 PARAMETER DEFINITION MIN MAX UNIT -65 150 °C TST Storage Temperature Range +150 °C TJ Junction Temperature MIN +260 °C TL Lead Temperature 6.5 kV HBM Human body model -0.3 2 V VESD MM Charger device model -0.3 500 0.5 7.3 Recommended Operating Conditions (Note 2) 0 -40 Input Voltages PARAMETER MAX Unit V Output Voltages VIN to GND 30 Output Current FB 6 V Temperature EN 6 A VOUT VIN*Dmax °C IOUT 3.1 Operating junction temperature range, TJ +125 7.4 Thermal Information (Note 3) Symbol Description ESOP-8 Unit θJA Junction to ambient thermal resistance 56 °C/W θJC Junction to case thermal resistance 45 Notes: 1) Exceeding these ratings may damage the device. 2) The device function is not guaranteed outside of the recommended operating conditions. 3) Measured on approximately 1” square of 1 oz copper. DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 7.5 Electrical Characteristics (Typical at Vin = 12V, TJ=25°C, unless otherwise noted.) SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT BUCK CONVERTER MOSFET RDS(ON)_H High-Side Switch On-Resistance IOUT = 1A, VOUT = 3.3V 76 mΩ IOUT = 1A, VOUT = 3.3V 52 mΩ RDS(ON)_L Low-Side Switch On-Resistance VFB =1.2V SUPPLY VOLTAGE (VIN) VUVLO_up Minimum input voltage for startup 6.5 V VUVLO_down 6.0 V VUVLO_hys 0.5 V IQ-NONSW Operating quiescent current 1 mA CONTROL LOOP 100 kHz Foscb Buck oscillator frequency 1.2 V VFB Feedback Voltage 1.1* VFB V 95 % VFB_OVP Feedback Over-voltage Threshold 200 ns Dmax Maximum Duty Cycle(Note 4) Ton Minimum On Time(Note 4) PROTECTION Iocl_hs Upper Switch Current Limit Minimum Duty Cycle 5.5 A Iocl_ls From Drain to Source 4.5 A Vinovp Lower Switch Current Limit 33 V Thsd 155 °C Thsdhys Input Over voltage protection 15 °C Dhiccup Thermal Shutdown(Note 4) 10 % Thermal Shutdown Hysteresis(Note 4) Hiccup duty cycle (Note 4) Note: 4) Guaranteed by design, not tested in production. DS-PL8322-Rev. 1.0 www.powlicon.com 4 of 16 2016-03-20 © Powlicon Inc.

PL8322 8 Typical Characteristics Vin = 12V, Vout = 5V Vin = 24V, Vout = 5V Fig. 3 Efficiency Fig. 4 Efficiency Vin = 12V, Vout = 5V Vin = 24V, Vout = 5V Fig. 5 Load transient 0.3A to 3A Fig. 6 Load transient 0.3A to 3A Vin = 12V, Vout = 5V Vin = 12V, Vout = 5V Fig. 7 Startup waveform, Iout = 0.3A Fig. 8 Startup waveform, Iout = 3A DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 Vin = 12V, Vout = 5V Vin = 12V, Vout = 5V Fig. 9 Shutdown waveform, Iout = 0.3A Fig. 10 Shutdown waveform, Iout = 3A Vin = 24V, Vout = 5V Vin = 24V, Vout = 5V Fig. 11 Startup waveform, Iout = 0.3A Fig. 12 Startup waveform, Iout =3A Vin = 24V, Vout = 5V Vin = 24V, Vout = 5V Fig. 13 Shut down waveform, Iout = 0.3A Fig. 14 Shutdown waveform, Iout = 3A DS-PL8322-Rev. 1.0 www.powlicon.com 6 of 16 2016-03-20 © Powlicon Inc.

PL8322 Vin = 12V, Vout = 5V Vin = 24V, Vout = 5V Fig. 15 Steady State, Iout = 3A Fig. 16 Steady State, Iout = 3A Vin = 12V, Vout = 5V Vin = 24V, Vout = 5V Fig. 17 Short Circuit waveform Fig. 18 Short Circuit waveform DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 9 Detailed Description 9.1 Overview PL8322 is an easy to use synchronous step-down DC-DC converter that operates from 6.5V to 30V supply voltage. It is capable of delivering up to 3.1A continuous load current with high efficiency and thermal performance in a very small solution size. PL8322 employs fixed frequency peak current mode control to regulate the output voltage. The device is internally compensated, which reduces design time, and requires fewer external components. The switching frequency is fixed at 100 kHz to minimize inductor size and improve EMI performance. 9.2 Functional Block Diagram BST SLEEP SleepREF SS COMP PowerDiode VIN High-Side V_Isns Current Sense VIN_N1 HSOCL VREG5 VIN_N2 SLEEP VINOV BANDGAP EN_Int VINUV \& VREG5UV PWM REFRENCE SW SDN Logic Dschg 1.2V HSOCL V_Isns HSOCREF 1.2V EN QR VINOV VIN_N2 IADJ GND S VINUV VINOVREF FB VREG5UV LSOCREF SLOPE VIN_N1 VINUVREF Low-Side IADJ CLK OSC Current \& VREG5UV Sense REF SLOPE VREG5 COMPENSATION GND Fig.19 PL8322 Diagram 9.3 Peak Current Mode Control PL8322 employs a fixed 100 kHz frequency peak current mode control. The output voltage is sensed by an external feedback resistor string on FB pin and fed to an internal error amplifier. The output of error amplifier will compare with high side current sense signal by an internal PWM comparator. When the second signal is higher than the first one, the PWM comparator will generate a turn-off signal to turn off high side switch. The output voltage of error amplifier will increase or decrease proportionally with the output load current. PL8322 has a cycle-by-cycle peak current limit feature inside to help maintain load current in a safe region. 9.4 CC/CV control mode and average load current limiting PL8322 has a CC/CV control mode. The load current is sensed and averaged. When average load current is high enough, constant-current loop will be dominant and limit the average load current to a value configured by resistor on IADJ pin. For decided average load current limit Iload, the resistor R3 can be calculated as equation (1): 1. (1) loa – . 1 R3 is the programming resistor on IADJ pin. The typical range is 10k-50k. DS-PL8322-Rev. 1.0 www.powlicon.com 8 of 16 2016-03-20 © Powlicon Inc.

PL8322 9.5 Line drop compensation When USB charging cable line is long and resistance is high, there will be some significant voltage drop on the cable. Portable device will see much lower input voltage. If the voltage across the load input terminals is too low, it will affect the charge time for the load. It is recommended to adjust the output voltage of charger to compensate this voltage drop. PL8322 has an excellent configurable line drop compensation feature. The line drop compensation value can be programmed by the top feedback resistor R1 in Fig 1. The value can be roughly calculated as equation (2): li e rop loa ls 1 (2) 1 Iload is the load current. Gls is the load current sense gain from load current to sourcing current on IADJ pin. R3 is the programming resistor on IADJ pin. R1 is the top output sensing resistor. For 5V/3.1A application, the values can be set as: R3=10k; R2=10k; R1=31.6k. Fig. 20 shows line drop compensation with different R1/R2 combinations. Fig. 20 line drop compensation 9.6 Sleep Operation for light load efficiency PL8322 has an internal feature to help improving light load efficiency. When output current is low, PL8322 will go into sleep mode to save power. 9.7 Setting Output Voltage The output voltage is set with a resistor divider from the output node to the FB pin. The 1% resistance accuracy of this resistor divider is preferred. The output voltage value is set as equation (3) below. It is recommended to make R2/R1=3.16: 1 (3) out ref Vref is the internal reference voltage of PL8322, which is 1.2V. 9.8 Error Amplifier The error amplifier compares the FB voltage against the internal reference (Vref) and outputs a current proportional to the difference between these two signals. This output current charges or discharges the internal compensation network to generate the error amplifier output voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control-loop design. 9.9 Slope Compensation In order to avoid sub-harmonic oscillation at high duty cycle, PL8322 adds a slope compensation ramp to the sensed signal of current flowing through high side switch. 9.10 Bootstrap Voltage provided by internal LDO PL8322 has an internal LDO to provide energy consumed by high side switch. At BST pin, PL8322 needs a small ceramic capacitor like 100nF between BST and SW pin to provide gate-drive voltage for high side switch. The bootstrap capacitor is charged when high side is off. In Continuous-Current-Mode, the bootstrap capacitor will be charged when low side is on. The bootstrap capacitor voltage will be maintained at about 5.3V. When IC works under sleep mode, what value the bootstrap capacitor is charged depends on the difference of Vin and output voltage. However, when the voltage on the bootstrap capacitor is below bootstrap voltage refresh threshold, PL8322 will force low side on to charge bootstrap capacitor. Connecting an external diode from the output of regulator to the BST pin will also work and increase the efficiency of the regulator when output is high enough. DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 9.11 Soft-Start Connect a capacitor on SS pin to program soft-start time. PL8322 has a soft-start function to control the ramp up speed of output voltage and limit the input current surge during IC start-up. . 9.12 Over-Current Protection and Hiccup PL8322 has cycle-by-cycle peak current limit for both high side and low side switch. When high side switch current is higher than high side current limit, high side switch will be turned off. PL8322 will not turn on high side switch again until low side switch current is lower than low side switch current limit. PL8322 has a CC/CV control structure. When load current is smaller than load current limit programmed by resistor on IADJ pin, CV (constant voltage) loop is dominant. FB voltage will be regulated to internal reference point. When load current is close to load current limit point, CC (constant current) loop will be dominant and regulate load current to be constant by lower down output voltage. If IADJ is connected to GND and output is shorted to GND, PL8322 will go into hiccup mode to limit average load current. PL8322 will exit hiccup mode once the over current condition is removed. 9.13 Thermal Shutdown The internal thermal-shutdown circuitry forces the device to stop switching if the junction temperature exceeds 155°C typically. When the junction temperature drops below 140°C, IC will start to work again. 9.14 Enable PL8322 can be enabled by EN pin. EN pin internal threshold is set at 1V. Customer can adjust the startup voltage at input pin by this EN pin through resistor divider. 10 Application and Implementation 10.1 Inductor selection An inductor is required to supply constant current to the load while being driven by the switched input voltage. A larger value inductor will result in less current ripple and lower output voltage ripple. However, the larger value inductor will have larger physical size, higher DC resistance, and/or lower saturation current. A good rule to calculate the inductance is to allow the peak-to-peak ripple current in the inductor to be approximately 25% of the maximum load current. At the same time, it is needed to make sure that the peak inductor current is below the inductor saturation current. The inductance value can be calculated by: fs 1- (4) Δ L is the peak-to-peak Where VOUT is the output voltage, VIN is the input voltage, fS is the switching freque cy, a inductor ripple current. Choose an inductor that will not saturate under the maximum peak current. The peak inductor current can be calculated by: loa fs 1- (5) Where Iload is the load current. The choice of inductor material mainly depends on the price vs. size requirements and EMI constraints. 10.2 Optional Schottky Diode During the transition between the high-side switch and low-side switch, the body diode of the low-side power MOSFET conducts the inductor current. The forward voltage of this body diode is high. An optional Schottky diode may be paralleled with low side MOSFET to improve overall efficiency. Table 2 lists example Schottky diodes and their Manufacturers. Table 2 – Diode Selection Guide Part Number Voltage/Current Rating Vendor SS25FA 50V/2A Fairchild B240A 40V/2A Vishay 10.3 Input capacitors selection The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the converter. It is recommend to use low ESR capacitors to optimize the performance. Ceramic capacitor is preferred, but tantalum or low-ESR electrolytic capacitors may also meet the requirements. It is better to choose X5R or X7R dielectrics when using ceramic capacitors. DS-PL8322-Rev. 1.0 www.powlicon.com 10 of 16 2016-03-20 © Powlicon Inc.

PL8322 Since the input capacitor (CIN) absorbs the input switching current, a good ripple current rating is required for the capacitor. The RMS current in the input capacitor can be estimated by: loa 1- (6) The worst-case condition occurs at VIN = 2×VOUT, where: (7) loa For simplification, choose the input capacitor whose RMS current rating is greater than half of the maximum load current. When electrolytic or tantalum capacitors are used, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When ceramic capacitors are used, make sure that they have enough capacitance to maintain voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: loa 1- (8) fs CIN is the input capacitance. 10.4 Output capacitors selection The output capacitor (COUT) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: fs 1- 1 (9) fs Where L is the inductor value, RESR is the equivalent series resistance (ESR) value of the output capacitor and COUT is the output capacitance value. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly determined by the capacitance. For simplification, the output voltage ripple can be estimated by: 1- (10) fs In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: fs 1- (11) The characteristics of the output capacitor also affect the stability of the regulator. PL8322is optimized for a wide range of capacitance and ESR values. 10.5 External bootstrap diode It is recommended that an external bootstrap diode could be added when the system has a 5V fixed input or the power supply generates a 5V output. This helps improve the efficiency of the regulator. The bootstrap diode can be a low cost one such as IN4148 or BAT54. 5V BST PL8322 SW Fig. 21 External Bootstrap Diode This diode is also recommended for high duty cycle operation (when (VOUT/VIN) > 65%) and high output voltage (VOUT>12V) applications. DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 11 PCB Layout 11.1 Guideline PCB layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion efficiency, thermal performance, and minimized EMI. 1. The feedback network, resistor R1 and R2, should be kept close to FB pin. Vout sense path should stay away from noisy nodes, such as SW and BST signals and preferably through a layer on the other side of shielding layer. 2. The input bypass capacitor C1 and C2 must be placed as close as possible to the VIN pin and ground. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the GND pin and PAD. It is a good practice to place a ceramic cap near the VIN pin to reduce the high frequency injection current. 3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise. 4. The output capacitor, COUT should be placed close to the junction of L and the diode D. The L, D, and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency. 5. The ground connection for C1, C2 and C3, C4 should be as small as possible and connect to system ground plane at only one spot (preferably at the COUT ground point) to minimize injecting noise into system ground plane. 6. Place current sense resister R3 as near as possible to the chip and stay away from noisy nodes such as SW, BST. 11.2 Example VIN/6.5V-30V 2 1 C5 L1 Vout/5V VIN BST 100nF/25V 22uH 3 R1 SW 31.6k C1 C2 5 1% C4 C3 100uF/50V 0.1uF/50V FB 0.1uF 100uF R2 EN 7 EN PL8322 10k 1% C6 47pF 8 IADJ 6 C7 SS R3 100nF/25V ADJ. GND 4 * C6 is optional. Fig. 22 Schematic Fig. 23 Top layer layout Fig. 24 Bottom layer layout DS-PL8322-Rev. 1.0 www.powlicon.com 12 of 16 2016-03-20 © Powlicon Inc.

VIN/6.5V-30V 2 1 C5 L1 Vout/5V PL8322 VIN BST 100nF/25V 22uH USB Port B 3 R1 VBUS SW 31.6k DM DP C1 C2 5 1% C4 C3 USB Port A GND 100uF/50V 0.1uF/50V FB 0.1uF 100uF VBUS R2 DM EN 7 EN PL8322 10k DP 1% GND C6 47pF 8 SS IADJ 6 C7 GND R3 100nF/25V 4 ADJ * C6 is optional. Fig. 25 Schematic for car charger Fig. 26 Top layer layout for car charger Fig. 27 Bottom layer layout for car charger DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.

PL8322 12 Packaging Information DS-PL8322-Rev. 1.0 www.powlicon.com 14 of 16 2016-03-20 © Powlicon Inc.

PL8322 13 Taping Orientation IMPORTANT NOTICE Powlicon Inc. assumes no responsibility for any errors which may appear in this document. Powlicon Inc. reserves the right to change devices or specifications detailed herein at any time without notice. Powlicon Inc. does not assume any liability arising out of the application or use of any product described herein; neither it does it convey any license under its patent rights, nor the rights of others. Powlicon Inc. products are not authorized for use as critical components in life support devices or systems without written approval letter from the Chief Executive Officer of Powlicon Inc.. The use of products in such applications shall assume all risks of such use and will agree to not hold against Powlicon Inc. for all damages. DS-PL8322-Rev. 1.0 www.powlicon.com 1of 315 2016-03-20 © Powlicon Inc.