MSquare Technology

COMPANY PROFILE

MSquare VISION

MEMORABILIA

HONORS

PRODUCTS OVERVIEW

HBM3 IP

D2D (UCIe) IP

LPDDR4X IP

LPDDR5X IP

ONFI 5.0 IP

ONFI 5.1 IP

eDP IP

PCIe 4.0 IP

USB 3.2 IP

ML100 IO Die

MSquare Technology, incorporated in 2021, is a leading provider of integrated circuit IPs and Chiplets, dedicated to

addressing the challenges of chip interconnectivity and vertical integration in the smart economy era. MSquare operates

offices in Shanghai, Taipei, Tokyo, Sydney, and San Jose， boasting a team of a few hundred employees, with 80% dedicated

to research and development. MSquare strives to foster an open ecosystem service platform for AI and Chiplets, providing

comprehensive support for innovation and development within the IC and Chiplet industry.

MSquare is named after the 2MASX occulting pair, a twin galaxy system comprising overlapping spiral galaxies whose

brilliant illumination extends six times their radius, guiding astronomers in observing surrounding galaxies. Inspired by this

phenomenon, MSquare aims to lead the semiconductor industry with cutting-edge products and services, striving to light

up the industry and cultivate a thriving, open ecosystem in collaboration with industry stakeholders.

COMPANY PROFILE

01

As a key technological leader upstream in semiconductor industry, MSquare scales the frontiers of chip design

technology through integrating system design, Chiplet Die, and custom services within the 2.5D OSAT alliance.

MSquare aspires to be pioneer in the AI era, focusing on the innovative research and development of

interconnect interface IPs and Chiplets across various fields, including AI, Data Centers, Automotive Electronics,

the IoT, and Consumer Electronics. By providing cutting-edge R&D and customized services for IPs and Chiplets,

MSquare is dedicated to leading industry standards and driving deep innovation in the hard core technology.

MSquare aims to forge a global leading Chiplet brand and pioneer the interconnected IP frontier. Leveraging a

comprehensive portfolio of IP products, MSquare is actively constructing a leading IP infrastructure platform to

drive AI and Chiplet technology innovation. MSquare's IP products have been successfully validated by notable

foundries process nodes and brought to mass production, spanning from 5nm to 180nm and covering over 400

different process nodes across 5 leading foundries. The R&D team has launched interconnect interface IPs

including HBM, LPDDR, ONFI, UCIe, eDP, PCIe, USB, as well as Chiplet solutions represented by M2LINK. MSquare

aims to build an open ecosystem service platform, continuously empowering digital transformation.

PRODUCT VISION

INDUSTRY VISION

02

MEMORABILIA

03

2021

MSquare Technology

Incorporated

Aug.

Office in San Jose, U.S. Established

Sept.

Pre-A Financing Completed

Nov.

PSRAM PHY Delivered

Dec.

MSquare Joined MIPI Alliance

Jan.

PCIe 4.0 12nm Tapeout

Feb.

PSRAM PHY First Customer Tapeout

Mar.

MSquare Joined UCIe Alliance

Apr.

MSquare Joined USB-IF Association

Jun.

MSquare Obtained ISO 9001

Certification

Aug.

ONFI 5.0 12nm Tapeout

Oct.

USB 3.2 12nm Tapeout

Jun.

Series A financing Completed

Dec.

2022

04

MSquare Joined CCITA Chiplet

Working Group

Jan.

LPDDR4X 12nm Tapeout

Feb.

Chiplet IO Die Ready

Jun.

ONFI5.1 5nm Delivered

Aug.

LPDDR5X 6nm Tapeout

May.

UCIe 12nm Tapeout

Sept.

MSquare Open Day

Jun.

Office in Brisbane, Australia Established

Aug.

ONFI5.1 12nm Delivered

LPDDR5X 6nm Delivered

HBM3 12nm Delivered

Oct.

MSquare Awarded

“Top 10 IP Company on

the Fabless 100 List”

Apr.

2023

2024

MSquare Awarded

“2023 Venture 50 List”

Jan.

MSquare Obtained ISO 26262:

2018 Certification

Feb.

CEO Awarded “2023 Most Noteworthy

Female Entrepreneur”

Mar.

MSquare Awarded “China's Top 100

Future Unicorns” and “Hard & Core

Technology Innovators”

Dec.

HONORS

05

Innovative IP Company of

the Year 2022 Top 20 Tech Cool Vendors

with the Most Commercial

Potential in the AI Field

2022 The Most Investment

Value Innovative Enterprise The Best Product Award

of 2023

2023 Most Noteworthy

Female Entrepreneur The Most Innovative

Products of 2023

The Best Employers of

2023

Hard & Core Technology

Innovators

2023 Venture 50

2023 Science & Technology

Good Company

2023 The Most Investment

Value Company

China's Top 100 Future

Unicorns

49+

Invention patent

10+

Layout patent

17+

Copyright & Trademark

30+

Awards

M2

Chiplet

D2D/UCIe M2LINK M2Chip IO Die Integration Service

PRODUCT OVERVIEW

High Speed

Interface IP

HBM LPDDR ONFI eDP PCIe USB

Processor Core Hardening+OPPA Interface IP Integration

IP Integration

and Harden

Service

Foundation

IP

Memory Compiler GPlO, Specialty IO Standard Cell

06

HBM3 IP PRODUCT INFO

07 For more process nodes, please contact us

OVERVIEW

MSquare's HBM3 IP (the 3 generation of High-Bandwidth Memory) is specifically tailored for applications

that require high memory throughput and low latency, complying with the JESD238 memory standard. It

includes both PHY and Memory Controller components, supporting HBM3 SDRAM speeds ranging from

4.8Gbps/pin to 6.4Gbps/pin. Flexible configurations are available, including PHY Only, PHY + Controller,

and Controller Only, to accommodate diverse customer design specifications. Additionally, the chip's

footprint and power consumption are highly competitive within the industry.

HIGHLIGHTS

Designed for high memory throughput and low latency applications

Figure 1: Block Diagram

Consists PHY and Memory Controller

Optimized for 12nm process

Supports speed up to 6.4Gbps/pin

Features integrated PLL and IO

Flexible configurations available: (PHY only) or (PHY + Controller) or (Controller only)

Supports both firmware-based training and hardware-based training

Optional Add-on IPs to achieve best performance

Minimized footprint and power consumption

NOC

NOC

NOC

Optional Add ons

X2C

CMDPATH

DATAPATH

CCS Host Interface (AXI4) PHY Interface (DFI/HFI)

HBM3MCTL HBM3PHY

PLL

ZCAL

DLL

PHY Micro

Controller

Aword Path

Dword Path

HBM3 I/O DFI/HFI Decoder

HBM3

DRAM

Stack

Host

Host

ASIC/FPGA

M2 HBM3 Host IP

rd

OVERVIEW

The Die-to-Die interface is a functional block that provides a data interface between two chip dies within

the same package. MSquare's D2D solution, compatible with the UCIe v1.1 specification, includes both a

Die-to-Die adapter layer and a physical layer. Each layer features a sideband interface that provides a

back-channel for link training and access to the registers of the link partner, as shown in Figure 1. This

unique hybrid analog/digital architecture offers low power consumption, compact footprint, and robust

performance, making it well-suited for target applications such as high-performance computing, AI, or

multimedia SoCs, and Die-to-Die interconnections.

Compatible with UCIe v1.1 specification

Features single-ended, source-synchronous, and DDR I/O signaling

Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages

Offers a high clock frequency up to 16GHz

Provides data transfer rate up to 32Gbps per lane

Delivers 1Tbps (512Gbps TX + 512Gbps RX) bandwidth per module for standard packages

High energy efficiency with ~0.8pJ/bit for standard packages

Built-in test and diagnostics [Functional (PRBS), scan, at-speed external loopback]

The advanced 12nm/6nm process

Figure 1: Architecture Diagram Figure 2: Block Diagram

DIE 0 DIE 1 (R180 of DIE 0)

UCle PHY

TX 16lane

RX 16lane

UCle PHY

TX 16lane

RX 16lane

UCle PHY

TX 16lane

RX 16lane

UCle PHY

TX 16lane Module3

RX 16lane

Module2 Module1 Module0

UCle

Adapter

Customer

Core

Logic

UCle PHY

UCle PHY

TX 16lane

RX 16lane

TX 16lane

RX 16lane

UCle PHY

TX 16lane

RX 16lane

UCle PHY

TX 16lane

RX 16lane

Module3 Module2 Module1 Module0

UCle

Adapter

Customer

Core

Logic

Substrate

32Gbps/lane

512Gbps TX + 512Gbps RX

Protocol Adapter DPHY APHY

Protocol Layer Adapter Layer Physical Layer

Sideband_

Prot

Sideband_

Adap

Sideband_

Phy

Flit aware

D2D interface

(FDI)

Raw D2D

interface

(RDI)

x16 MB Data

Forward CLK

SB Data

Forward CLK

08

D2D (UCIe) IP PRODUCT INFO

For more process nodes, please contact us

HIGHLIGHTS

LPDDR4X IP PRODUCT INFO

MSquare's LPDDR4X PHY is a transceiver physical layer IP interface solution designed for ASICs and

SOCs. Compatible with the universal IP protocol DFI 4.0, it operates at a data rate of up to 4267Mbps with

a 16-bit data width per channel. As depicted in Figure 1, the LPDDR4X PHY block diagram for system

application includes a data and address transmit path, a receiver data path, a PLL block, and more.

Featuring a hybrid analog/digital architecture, MSquare's IP delivers low power consumption, a compact

footprint, and robust performance, making it well-suited for LPDDR4X applications.

Compatible with LPDDR4X, with a maximum rate up to 4267Mbps

Compliant with DFI 4.0 for PHY and control interfaces

Flexible channel architecture

Supports PHY-independent training mode using an embedded processor

Supports dual rank

DFS supports 4 trained frequencies

Supports BIST and loopback modes

Supports background tracking for PVT compensation

Integrated low-jitter PLL and DLL

Compliant with JEDEC standard JESD209-4C

Figure 1: System-Level Block Diagram

DRAM

Device

Interface

MC

DFI 4.0

LPDDR4X

Soft_PHY DFI Interface 4.0

ACP2S

DP2S

DS2P

AC_TX

DATA_TX

DATA_RX

PIPE_AC Address Macro

Data Macro

PLL,DLL,other logic

PIPE_TX

PIPE_RX

BIST etc.

09 For more process nodes, please contact us

OVERVIEW

HIGHLIGHTS

LPDDR5X IP PRODUCT INFO

OVERVIEW

MSquare's LPDDR5X/4X PHY is a transceiver physical layer IP interface solution designed for ASICs and

SOCs. Compatible with the universal IP protocol DFI 5.0, it operates at data rates up to 8533Mbps with a

16-bit data width per channel. With flexible configuration options, the LPDDR5X/4X PHY supports a

variety of mobile applications using LPDDR5X, LPDDR5, and LPDDR4X SDRAMs. Featuring a hybrid

analog/digital architecture, MSquare's IP delivers low power consumption, compact footprint, and robust

performance, making it well-suited for LPDDR5X/4X applications.

HIGHLIGHTS

Compatible with JEDEC standards LPDDR4X, LPDDR5 and LPDDR5X SDRAMs

Supports for data transfer rate up to 8533Mbps

DFI 5.0 for PHY and controller interfaces

Supports both firmware-based training and hardware-based training

Supports multiple gears of DFS

High performance, low jitter DDR IO

Single Tap DFE for Channel Robustness

Supports 4 trained frequencies

User-customizable arbiter (scheduler)

Compliant with JEDEC standards JESD209-4D and JESD209-5B

Figure 1: System-Level Block Diagram

For more process nodes, please contact us 10

LPDDR LPDDR PHY

Controller

CK

Domain

WCK

Domain

Memory

Array

LPDDR5X

Device

BIST

HW

Training

Engine DLL

FSP

DCM

Power

Mqr

MCU

CMD/ADDR

Block

Data Block

DDR IO DFI LogicDFI Interface DRAM CA and Data

PLL

AXI TX

AXI RX

Arbitration

System

Control

Logic

ONFI PHY

ONFI 5.0 IP PRODUCT INFO

OVERVIEW

MSquare offers a silicon-proven ONFI 5.0 PHY IP that supports all modes of the Open NAND Flash

Interface (ONFI) 5.0 specification. ONFI is an interface that connects external flash particles (NAND

Flash) and internal flash controller (NAND Controller), commonly used in Solid State Drives (SSD) and

embedded memory (eMMC) products. To facilitate customer implementation, the MSquare's ONFI 5.0

PHY supports expandable channels and customizable CE/RB Pad Numbers.

HIGHLIGHTS

Compliant with ONFI 5.0 specification

Supports NV-DDR2 mode

Supports NV-DDR3, NV-LPDDR4, with a maximum rate of 2400MT/s

Supports PHY Independent TX/RX Training mode

Supports DFI with 1:1 / 1:2 clock ratio mode

Supports self-test mode with built-in BIST

Supports loopback test with built-in PRBS

Supports ODT programmable and ZQ calibration

Integrated low-jitter PLL & DLL

Figure 1: Architecture Diagram Figure 2: Block Diagram

PHYD PHYA IO

Processor or Main chip

eMMC I/O,UFS,SATA and etc

SSD/eMMC

Flash ONFI interface

controller Flash memory

array

For more process nodes, please contact us

PHY_reg

Build-in

Bist Training

Ctrl path

Data path

Ctrl slice

Ctrl IO

Data slice

DLL PLL Data

IO

11

ONFI 5.1 IP PRODUCT INFO

OVERVIEW

HIGHLIGHTS

Compliant with ONFI 5.1 specification

Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s

Supports matched or unmatched DQS

Supports WDCA/Per-Pin VREFQ Training for NAND devices

Supports WT Monitor

Supports Separate Command Address (SCA) to improve NAND IO efficiency

Supports 2 channels with a single PHY PLL & flexible floorplan with double or single row IO

Supports DFI with 1:1 / 1:2 clock ratio mode

Supports TX/RX Training mode

Delay-Chain supports background tracking for PVT compensation

Test Mode: Self-test mode with built-in BIST & Loopback test with built-in PRBS & BIST-Delay-Chain

Figure 1: Architecture Diagram Figure 2: Block Diagram

Processor or Main chip

eMMC I/O,UFS,SATA and etc

SSD/eMMC

Flash ONFI interface

controller Flash memory

array

ONFI PHY

PHYD PHYA IO

Ctrl IO

PHY_reg

Build-in

Bist Training

Ctrl path

Data path

Ctrl slice

Data slice

DLL PLL Data

IO

For more process nodes, please contact us

MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the

Open NAND Flash Interface (ONFI) 5.1 specification. ONFI is an interface connecting external flash

particles (NAND Flash) and internal flash controller (NAND Controller), widely used in Solid State Drive

(SSD) products. To simplify the implementation, MSquare ONFI 5.1 PHY supports expandable channels

and customizable CE/RB pad numbers.

12

eDP IP PRODUCT INFO

13 For more process nodes, please contact us

OVERVIEW

HIGHLIGHTS

Compatible with embedded display port v1.5/v1.4b specification

Figure 1: System-Level Block Diagram

Four-lane main link with support for 8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps

Supports Enhanced Framing Mode

Automatic Link-Training with an option for firmware-controlled Link-Training procedure

Supports Fast Link Training/No Link Training

Supports AUX Channel for access to DPCD and EDID

Supports a maximum 144Hz refresh rate

Supports variable refresh rate and Adaptive-Sync for VESA Adaptive Sync

Supports Panel Self Refresh (PSR) function and PSR with selective update (PSR2) function

Supports VESA DSC v1.01, v1.1, v1.2a with FEC

Supports Panel Replay (PR) and Adaptive Refresh Panel (APR)

Image buffer

Logic

AUX CH

Com

Logic

Decode

DPCD

EDID

PSR

M-Touch

BackLight

RX Bit Recovery Lock

Image

Framebuffer

Display

Main Link

Hot Plug

Detect

AUX

TX

Driver

MSquare's eDP PHY is a highly reliable solution for display interface requirements, supporting resolutions

of 4K and higher. By operating at substantially higher bit rates, this eDP solution reduces both the number

of wires and pins required compared to interfaces like LVDS, DVI, and HDMI. It is fully compliant with eDP

v1.5 and v1.4b standards, and capable of driving up to 8.1Gb/s per lane in configurations up to 4 lanes. It

consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP. MSquare provides eDP with

superior PPA and offers customization based on customer specifications.

OVERVIEW

MSquare's PCI Express 4.0 PHY IP includes a high-speed, highly-efficient, and cost-effective transceiver

to turbocharge today's high-performance and high-bandwidth applications such as data centers,

automotive, enterprise computing, and high-performance embedded systems.

The PCIe IP boasts a low power consumption and compact silicon footprint. Its robust PHY architecture

tolerates process, voltage, and temperature (PVT) variations. This IP integrates high-speed mixed-signal

circuits to support PCIe 4.0 traffic at 16Gbps. It is backward compatible with PCIe 3.1 data rates at

8.0Gbps, PCIe 2.1 at 5.0Gbps, and PCIe 1.1 at 2.5Gbps. The multi-tab transceiver design, accompanied

by a robust BIST, an embedded bit error rate (BER) tester, and an internal eye monitor, enables designers

to control, test, and monitor signal integrity without the need for expensive test equipment.

HIGHLIGHTS

Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications

Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications

Supports L1 PM/CPM substates with CLKREQ#

Supports the separate REFCLK Independent SSC (SRIS) architecture

Accessible register control TX PLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength

Supports both FOM and DIR modes for Link-EQ Training

Supports robust BIST/DFT functions for mass production tests

Supports bifurcation with 4-lane x 1 or 2-lane x 2 configurations

Figure 1: Block Diagram Figure 2: Chip Layout

pattem

checker

RX Logic 8b/10b128b

/130b

Decoder

Elastic

Buffer Deserilizer EQ/CDR

TX

Driver Serializer

Clock Multiplying Units

8b/10b

128b/130b

Encoder

TX Logic

Pattem

Generator

RXDP

RXDM

REFCLKM

TXDP

TXDM

REFCLKP +

-

MUX

32 bit @500MHz

32bit @500MHz

Control

/status

Rate

-

+

PCIe 4.0 IP PRODUCT INFO

For more process nodes, please contact us 14 PCIe 4.0 Controller

OVERVIEW

MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB 2.0 specifications from

the USB Implementers Forum and delivers bandwidth up to 10Gbps. This high bandwidth capability is

particularly beneficial for consumer and industrial video applications, as well as display, docking, cloud

computing, and automotive applications.

As a leading supplier of USB IP, MSquare offers customers low-power, compact, and high-performance

IPs featuring a unique hybrid analog/digital architecture. This IP supports all USB functions, including

transceivers for 10G, 5G, 480M, 12M, and 1.5Mbps. It provides complete deliverables that simplify SoC

integration and silicon validation. Available in a wide variety of process nodes from 40nm to 6/7nm, this IP

features a compact die size and low pad count, enhancing product competitiveness in the USB market.

HIGHLIGHTS

Fully compliant with USB 3.2 Gen2x1 featuring PIPE 4.3 and USB 2.0 with a UTMI+ interface

Figure 1: Architecture Diagram Figure 2: Chip Layout

Patternche

Checker

RX Logic 8b/10b

128b/132b

Decoder

Deserilizer

8b/10b

128b/132b

Encoder

TX Logic

Pattem

Generator

MUX MUX DEMUX MUX

CC1

SSRXP0

SSRXM0

SSRXP1

SSRXM1

SSTXP0

SSTXM0

SSTXP1

SSTXM1

CC2

USB 2.0 PHY DP DP

DP

PLL And

Clock Generator

Crystal/

Coreclkin

DP

PIPE

Elastic

Buffer

UTMI+

Crystal /

Coreclkin

Serializer TX Driver

Serializer TX Driver

EQ/CDR

CC SSCG-PLL Module

Supports host, peripheral, and dual-role applications

Supports 10/12/25/30/19.2/24/27/40MHz crystal oscillators or clock inputs

Supports TX 3-Tap FFE and RX CTLE+1-Tap DFE for SS+

Integrates an active switch to support orientation-less connections with the USB Type-C connector

Provides an auxiliary CC module IP for USB Type-C related functions

Offers robust BIST functions for mass production tests

Supports a crystal pad for clock source, compatible with MSquare's XTAL module IP

Supports OTG applications, compatible with MSquare's IDPAD module IP

Available in 7nm, 12nm, 16nm, 28nm, and 40nm processes

Supports both wire-bond and flip-chip package types

USB 3.2 IP PRODUCT INFO

15 For more process nodes, please contact us

For more process nodes, please contact us 16

ML100 IO Die PRODUCT INFO

OVERVIEW

HIGHLIGHTS

Figure 1: Block Diagram

SOC Die

(High Speed

UCIe Interface) HBM3 6.4G

DRAM

HBM3

PHY

HBM3

Ctrl

AXI 4.0

BUS

Moniter

VT

Sensor

I2C QSPI Jtag

GPIO UART QSPI I2C

Nor

Flash

RV-CPU

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

Adapter Protocol Adapter Protocol Adapter Protocol Adapter Protocol

APB

Mainband

Sideband

APB AHB-BUS

MSquare's ML100 IO Die is a high-bandwidth memory solution that integrates efficient UCIe (Die-to-Die)

interconnect IP and HBM3 IP. The UCIe IP follows the UCIe 1.1 Specification and supports both standard

and advanced packaging technologies, offering up to 1 TB/s of transfer bandwidth in a single module

configuration. The UCIe supports the AXI4.0 interface standard, enabling ultra-low latency, high-speed

interconnectivity between two dies. And the integrated HBM3 IP adheres to the HBM3 JESD238 standard

and supports IO transfer rates of up to 6400 Mbps.

Integrates 16 complete UCIe modules, following the standard UCIe 1.1 standard

Integrates one complete HBM3 IP, including the controller and PHY, following the HBM3 JESD238 standard

Supports interconnectivity with the SoC via the AMBA AXI4.0 standard

The AXI4.0 bus supports bandwidth traffic and latency statistics

Supports various peripherals, i.e., NOR Flash, QSPI, I2C and UART

Maximum bandwidth is 819.2 GB/s, matching the bandwidth of 6400 Mbps HBM3 DRAM

Utilizes a 2.5D packaging solution, interconnected with the SoC through substrate

Decouples the HBM from the SOC, reducing the thermal effect on HBM DRAM

www.m2ipm2.com

E-mail: marcom@m2ipm2.com

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