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MSquare Technology
CONTENT
COMPANY PROFILE
MSquare VISION
MILESTONES 03
HONORS 05
INTELLECTUALPROPERTY 06
PRODUCTS OVERVIEW 07
⊚ ML100 I0 Die 08
HBM3 IP 09
D2D (UCle) IP 10
\bullet ONFI5.0 IP 1
\bullet ONFI5.1 IP 2
⊚ LPDDR4X IP 13
⊚ LPDDR5X IP 14
eDPIP 15
\bullet PCle 4.0 IP 16
COMPANYPROFILE
MSquarehlgyrtdsdinidfinratdcircuindhtdia addresingthechallengesfchipinterconnectivitandverticalintegrationinthemarteconmyeraMquareperat officesinhanghaiokyydeyndanJoseboastingateamffwhundredemloyeeith 80% dedicatedto researchanddevepmentMquarestrivetfostranpencosstmservicelafrmorlandChipetsprovidin comprehensive support for innovation and development within the IC and Chiplet industry.
MSquaresnamedafetheccultingpairatingalaxystmcomprisinverlappingsiralgalaxiswhei liantilumnatinextedssixtimestherradusuiingasronmerinberinurrundinggalaxiepirdbthi phenomnquaeadthicndtndstwihci-dprdtsnevitrivinli uptheindustryand cultivateathriving,openecosystemincollaborationwithindustrystakeholders.
INDUSTRYVISION
AsakeytchlgicaadepstreammicnutrndustryMqurecalesthrotiefchipdesigtehly throughntgratingsystemdesiChltDiandcustmservicewithinthe.DATallinceMquareaspires pineerinthelerafocusingntheinnovativreearchanddevelpmntfinterconnectinterfaceandChpts acrossariusfildldinatenterAmtivlrnishannurtroncprvi cutting-dndcustmizedsrviceandChletMquaeicatedteadingindstrstadadd driving deep innovation in the hard core technology.
PRODUCTVISION
MSquareaimstofrgeagloballeadingChipletbrandandpioneertheinterconectedIfrontierLeveragingcomrehnsiveporfolifprdtquarectivlnstrutingedinnfrastruturelaormtrivndhl technologyinvationquareprdutshaveeensuccessfullyaldatdbytablefoundripressnded broughttomassproduction,spanningfrom5nmto 180\mathsf{n m} andcoveringover400differentprocessnodesacross5leading fundrie&masahdinrctntfanM welasChipletolutionrpresentedbyquareamtbuildanpncsystemserviceplatfomontinus empowering digital transformation.
2021
Aug. MSquare Technology Incorporated
Sept. OfficeinSan Jose,U.S.Established
Nov.
Completed Pre-A Round Financing
Dec. PSRAMPHYDelivered
2022
Jan. MSquareJoinedMIPIAlliance
Apr. MSquare Joined UCle Alliance
Jun. MSquareJoined USB-IFAssociation
Aug.
MSquareObtainedISO9001 Certification
Dec. Completed Series A Round Financing
Feb. PCle 4.0 12nm Tapeout
Mar. PSRAMPHYFirstCustomerTapeout
Jun. USB 3.2 12nm Tapeout
Oct. ONFI 5.0 12nm Tapeout
2023
Jan. MSquareJoinedCCITA Chiplet Working Group
Mar.
CEOAwarded"2023Most NoteworthyFemale
Entrepreneur"
Jun. MSquare Open Day
Aug. Office in Sydney, AustraliaEstablished
Dec. MSquareAwarded "China's Top 100 Future Unicorns"and"Hard & CoreTechnologyInnovators"
Feb. LPDDR4X 12nm Tapeout
May. LPDDR5X6nmTapeout
Sept. UCle 12nm Tapeout
Oct. ONFI5.112nmDelivered LPDDR5X6nmDelivered HBM312nmDelivered
2024
Jan. MSquareAwarded "2023Venture50List"
Feb.
MSquareObtainedISO26262: 2018Certification Apr.
MSquareAwarded“Top10 IP Company on the Fabless 100List" Nov.
MSquareAwarded
"Outstanding Innovative Companyof theYear"at 2024WEAA
Nov.
UCle 6nm Tapeout
Dec. ONFI 6.0 8nmTapeout LPDDR5X 8nm Tapeout ONFI5.15nmSiliconProven
2025
Apr.
MSquareAwarded "MostInnovativeTech StartupoftheYear" and "MostInnovative WomanoftheYear" atAsia-Pacific Stevie ⑧ Awards
Feb. ML1001ODieDelivered
17
INTELLECTUALPROPERTY
ISO CERTIFICATIONS
PRODUCTOVERVIEW
OVERVIEW
MSquare'sML100IODieisahigh-bandwidthmemorysolutionthat integratesefficientUCle(Die-to-Die) interconnect IPand HBM3IP.TheUCleIPfollows theUCle1.1Specificationand supportsbothstandard andadvancedpackagingtechnologiesofferingupto1B/sof transferbandwidthinasinglemodule configuration.The UCle supports the {\mathsf{A X}}|4.0 interfacestandard,enablingultra-lowlatency,high-speed interconnectivitybetweentwodies.AndtheintegratedHBM3IPadherestotheHBM3JESD238standard andsupportsIOtransferratesof upto6400Mbps.
| Integrates16completeUClemodules,following thestandardUCle1.1standard |
| IntegratesonecompleteHMPincludingthcontrollerandPHfllwingthBM3JD38standard |
| SupportsinterconnectivitywiththeSOCviatheAMBAAXI4.0standard |
| TheAXl4.0bussupportsbandwidthtrafficand latencystatistics |
| Supportsvariousperipherals,ie,ORFlash,QPI2CandART |
| Maximumbandwidthis819.2GB/s,matchingthebandwidthof6400MbpsHBM3DRAM |
| Utilizesa2.5Dpackagingsolution,UCleinterconnectedwiththeSOCthroughsubstrate |
| DecouplestheHBMfromtheSOC,reducingthethermaleffectfromSOCtoHBMDRAM |
OVERVIEW
MSquare'sHBM3IP(the 3^{\mathsf{r d}} generationofHigh-BandwidthMemory)isspecificallytailoredforapplications thatrequirehighmemorythroughputandlowlatencycomplyingwiththeJESD238memorystandard.lt includesbothPHYandMemoryControllercomponents,supportingHBM3SDRAMspeedsranging from 4.8Gbps/pinto6.4Gbps/pin.Flexibleconfigurationsareavailable,includingPHYOnly,PHY ^+ Controller, andControllerOnlytoaccommodatediversecustomerdesignspecifications.Additionally,thechip's footprintandpowerconsumptionarehighlycompetitivewithintheindustry.
| Designedforhighmemorythroughputandlowlatencyapplications |
| ConsistsPHYandMemoryController |
| Optimizedfor12nmprocess |
| Supportsspeedupto6.4Gbps/pin |
| FeaturesintegratedPLLandIO |
| Flexible configurations available:(PHYonly)or(PHY+Controller)or(Controlleronly) |
| Supportsbothfirmware-based trainingandhardware-based training |
| Optional Add-onIPstoachievebestperformance |
| Minimizedfootprintandpowerconsumption |
OVERVIEW
TheDie-to-Dieinterfaceisafunctionalblockthatprovidesadatainterfacebetweentwochipdieswithin thesamepackageMSquareDDsolutioncompatiblewiththeCle.secificationncludesboth Die-to-Dieadapterlayerandaphysicallayer.Eachlayerfeaturesasidebandinterfacethatprovidesa back-channelforlinktraining andaccesstotheregistersof thelinkpartnerasshowninFigure.his uniquehybridanalog/digitalarchitectureofferslowpowerconsumptioncompactfootprintandrobust performancemakingitwell-suitedfortargetapplicationssuchashigh-erfrmancecomputingr multimediaSoCs,andDie-to-Dieinterconnections.
| CompatiblewithUClev1.1specification |
| Featuressingle-ended,source-synchronous,andDDR/Osignaling |
| Supports32-bit(16-bitsTX+16-bitRX)databuspermoduleforstandardpackages |
| Offersahighclockfrequencyupto16GHz |
| Providesdatatransferrateupto32Gbpsperlane |
| Delivers1Tbps(512GbpsTX+512GbpsRX)bandwidthpermoduleforstandardpackages |
| Highenergyeficiencywith~0.8pJ/bit forstandardpackages |
| Built-intestand diagnostics[Functional(PRBS),scan,at-speedexternal loopback] |
| Theadvanced12nm/6nmprocess |
MSquareoffersa silicon-provenONFI5.0PHYIPthatsupportsallmodesof theOpenNANDFlash Interface(ONFI)5.0specification.ONFIisaninterface that connectsexternal flashparticles(NAND Flash)and internalflashcontroller(NAND Controller),commonlyused inSolidStateDrives(SSD）and embeddedmemory(eMMC)products.Tofacilitatecustomerimplementation,theMSquare'sONFI5.0 PHYsupportsexpandablechannelsandcustomizableCE/RBPadNumbers.
| CompliantwithONFI5.0specification |
| SupportsNV-DDR2mode |
| SupportsNV-DDR3,NV-LPDDR4,withamaximumrateof2400MT/s |
| SupportsPHYIndependentTX/RXTrainingmode |
| SupportsDFIwith1:1/1:2clockratiomode |
| Supportsself-testmodewithbuilt-inBIST |
| Supportsloopbacktestwithbuilt-inPRBS |
| SupportsODTprogrammableandZQcalibration |
| Integratedlow-jitterPLL&DLL |
OVERVIEW
MSquare'sONFI5.1PHYisahigh-performanceandlow-powerPHYIPwhichsupportsallmodesof the OpenNANDFlashInterface(ONFI)5.1specification.ONFIisan interface connecting external flash particles(NANDFlash)and internalflashcontroller(NANDController),widelyusedinSolidStateDrive (SSD）products.Tosimplifytheimplementation,MSquareONFI5.1PHYsupportsexpandablechannels andcustomizableCE/RBpadnumbers.
HIGHLIGHTS
| CompliantwithONFI5.1specification |
| SupportsNV-DDR3/NV-LPDDR4,withamaximumrateupto3600MT/s |
| SupportsmatchedorunmatchedDQS |
| SupportsWDCA/Per-PinVREFQTrainingforNANDdevices |
| SupportsWTMonitor |
| SupportsSeparateCommandAddress(SCA)toimproveNANDIOefficiency |
| Supports2channelswithasinglePHYPLL&flexiblefloorplanwithdoubleorsinglerowIO |
| SupportsDFIwith1:1/1:2clockratiomode |
| SupportsTX/RxTrainingmode |
| Delay-ChainsupportsbackgroundtrackingforPVTcompensation |
| TestMode:Self-testmodewithbuiltinBIST&Loopbacktestwithbuilt-inPRBS&BIST-Delay-Chain |
MSquare'sLPDDR4XPHYisatransceiverphysical layerIPinterfacesolutiondesignedforASICsand SOCs.CompatiblewiththeuniversalIPprotocolDFI4.0itperatesatadatarateofupto4267Mbpswith a16-bitdatawidthperchannel.AsdepictedinFigure1,theLPDDR4XPHYblockdiagramforsystem applicationincludesadataandaddresstransmitpath,areceiverdatapath,aPLLblockandmore. Featuringahybridanalog/digitlarchitcturequarePdeliverslwpowerconumptionompat footprint,androbustperformance,makingitwell-suitedforLPDDR4Xapplications.
HIGHLIGHTS
| CompatiblewithLPDDR4X,withamaximumrateupto4267Mbps |
| CompliantwithDFI4.0forPHYandcontrolinterfaces |
| Flexiblechannelarchitecture |
| SupportsPHY-independent trainingmodeusing anembeddedprocessor |
| Supportsdualrank |
| DFSsupports4trainedfrequencies |
| SupportsBISTand loopbackmodes |
| SupportsbackgroundtrackingforPVTcompensation |
| Integratedlow-jitterPLLandDLL |
| CompliantwithJEDECstandardJESD209-4C |
OVERVIEW
MSquare'sLPDDR5X/4XPHYisatransceiverphysicallayerIPinterfacesolutiondesigned forASICsand SOCs.CompatiblewiththeuniversalIPprotocolDFI5.0,itoperatesatdataratesupto8533Mbpswitha 16-bit datawidthperchannel.Withflexible configurationoptions,theLPDDR5X/4XPHYsupportsa varietyofmobileapplicationsusingLPDDR5X,LPDDR5andLPDDR4XSDRAMs.Featuringahybrid analogdigitlarchitcturequaredliverswpowerconsumptioncompactfootprintandrobust performance,makingitwell-suitedforLPDDR5X/4Xapplications.
HIGHLIGHTS
| CompatiblewithJEDECstandardsLPDDR4X，LPDDR5andLPDDR5XSDRAMs |
| Supportsfordatatransferrateupto8533Mbps |
| DFI5.0forPHYand controllerinterfaces |
| Supportsbothfirmware-basedtraining and hardware-based training |
| SupportsmultiplegearsofDFS |
| Highperformance,lowjitterDDRIO |
| SingleTapDFEforChannel Robustness |
| Supports4trainedfrequencies |
| User-customizable arbiter(scheduler) |
| CompliantwithJEDECstandardsJESD209-4DandJESD209-5B |
MSquareseDPPHisahighlyreliablesolutionfordisplayintefacerequirementssupportingresolutions of4KandhigherByoperatingatsubstantiallyhigherbitratesthisDPsolutionreducesboththenumber ofwiresandpinsrequiredcomparedtointerfacelieDDVandMtisfullycompliantwith v1.5and1.4bstandards,andcapableofdrivingupto8.1Gb/sperlaneinconfigurationsupto4lanes.l consistsofelectricalsub-blocksofmain-linkandAUXchannelofPHYforeDP.MSquareprovideseDPwith superiorPPAandofferscustomizationbased oncustomerspecifications.
HIGHLIGHTS
| Compatiblewithembeddeddisplayportv1.5/v1.4bspecification |
| Four-lanemain linkwith support for8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps |
| SupportsEnhancedFramingMode |
| AutomaticLink-Trainingwithanoptionforfirmware-controlledLink-Trainingprocedure |
| SupportsFast LinkTraining/NoLinkTraining |
| SupportsAUXChannel foraccesstoDPCDand EDID |
| Supportsamaximum144Hzrefreshrate |
| SupportsvariablerefreshrateandAdaptive-SyncforVESAAdaptiveSync |
| SupportsPanel Self Refresh(PSR)function andPSRwithselective update(PSR2)function |
| SupportsVESADSCv1.01,v1.1,v1.2awithFEC |
| SupportsPanel Replay(PR)and AdaptiveRefreshPanel(APR) |
PCle 4.0 IP
OVERVIEW
MSquaresIExpress4HPnludeshig-speedighly-ficetndcost-effectivetrans toturbochargetoday'shigh-performanceandhigh-bandwidthapplicationssuchasdatacentersautomotive,enterprisecomputing,andhigh-performanceembeddedsystems.
ThePCleIPboastsalowpowerconsumptionandcompactsiliconfootprintItsrobustPHYarchitecture toleratesprocessvoltageandtmeratureT)variationshisPintrateshigh-speedmixed-sia circuitstosupportPCle4.0 trafficat16Gbps.It isbackwardcompatiblewithPCle3.1datarates at 8.0Gbps,PCle2.1at5Gbps,andPCle1.1at2.5Gbps.hemulti-tabtransceiverdesign,accompanid byarobustnmbddbitrrorrateestrandanintealymnitrnabldsig tocontrol,test,andmonitorsignalintegritywithouttheneedforexpensivetestequipment
HIGHLIGHTS
| Compiles withPCle4.0,3.1,2.1,1.1andPIPE4.4.1 specifications |
| Supportsallpower-saving modes(P0,POs,P1,P2)asdefined inPIPE4.4.1specifications |
| SupportsL1PM/CPMsubstateswithCLKREQ# |
| SupportstheseparateREFCLKIndependentSSC(SRIS)architecture |
| AccessiblergistercontrolTPLLbandwidthTXde-mphasievelDRbandwidthandEQstrength |
| SupportsbothFOMandDIRmodesfor Link-EQTraining |
| SupportsrobustBIST/DFTfunctionsformassproductiontests |
| Supportsbifurcationwith4-lanex1or2-lanex2configurations |
MSquare E-Book
Chiplets Interconnection Blazing, Massive Computing Wellspring.
www.m2ipm2.com
