奎芯科技 MSquare Technology

目录 CONTENT

公司简介 01
行业愿景 02
大事记 03
公司荣誉 05
知识产权 06
产品综述 07
⊚ ML100 I0 Die 08
⊚ HBM3 IP 09
⊚ D2D (UCle) IP 10
⊚ ONFI5.0 IP 1
⊚ ONFI5.1IP 12
⊚ LPDDR4X IP 3
⊚ LPDDR5X IP 14
⊚ eDP IP 15
⊚ PCle 4.0 IP 16

公司简介

奎芯科技（MSquareTechnology）于2021年注册成立，是一家专业的集成电路IP和Chiplet产品供应商。公司专注于解决智慧经济时代下芯片互联和应用垂直整合的挑战。目前在上海，东京，悉尼，圣何塞等地拥有办公室，拥有一支数百人的团队，其中研发人员占比高达 80% 奎芯科技致力于构建一个AI与Chiplet的开放生态服务平台，旨在为集成芯片和芯粒产业的创新和发展提供全方位的支持。奎芯科技（MSquareTechnology）命名来自于双胞胎星系。该星系由两个重叠的螺旋星系构成，其闪耀的光芒照亮了其半径6倍的区域，天文学家借助它的指引观察周围的星系。奎芯科技以此自喻，期望凭借先进的的产品和服务引领半导体产业的繁荣和发展，与产业链上下游共同打造共赢且开放的生态，照亮整个半导体领域。

作为半导体产业链上游的技术引领者，奎芯科技通过整合系统设计、ChipletDie及2.5D封装联盟的定制业务，勇攀芯片设计技术的巅峰。我们立志成为AI时代的先锋领航者，专注于互联接口IP与Chiplet产品的创新研发，广泛覆盖人工智能、数据中心、汽车电子、物联网及消费类电子等多元领域。通过提供先进的半导体IP和Chiplet研发与定制服务，奎芯科技致力于打造一个开放、协同的生态体系，以引领行业标准，推动硬科技创新的深层发展。

产品愿景

PRODUCTVISION

奎芯科技旨在打造国际芯粒品牌，成就互联IP龙头。凭借丰富的IP产品组合和先进的技术实力，奎芯科技正积极构建业界领先的IP基础设施平台，引领AI与Chiplet技术创新。奎芯科技的IP已经成功在一些知名厂商的工艺节点得到验证并实现量产，目前已成功开发5nm到1 |80\mathsf{n m} 、覆盖五大晶圆厂的400多个不同制程节点的IP产品。研发团队已陆续推出UCle、HBM、LPDDR、ONFI、eDP、PCle、USB等互联接口IP，以及以M2LINK为代表的Chiplet产品解决方案，打造开放生态的服务平台，持续赋能数字化转型。

10月 ONFI5.112nm交付 LPDDR5X 6nm交付 HBM312nm交付

国际认证体系

ISOCERTIFICATIONS

HIGHLIGHTS

MSquare'sML100IODieisahigh-bandwidthmemorysolutionthatintegratesefficientUCle(Die-to-Die) interconnect IPand HBM3IP.TheUCleIPfollowstheUCle1.1Specificationandsupportsbothstandard andadvancedpackagingtechnologiesofferingupto1TB/softransferbandwidthinasinglemodule configuration.TheUClesupportsthe {\mathsf{A X}}|4.0 interfacestandard,enablingultra-lowlatency,high-speed interconnectivitybetweentwodies.AndtheintegratedHBM3IPadherestotheHBM3JESD238standard andsupportsIOtransferratesofupto6400Mbps.

Figure 1:BlockDiagram

MSquare'sHBM3IP(the 3^{\mathsf{r d}} generationof High-BandwidthMemory)isspecificallytailoredforapplications thatrequirehighmemorythroughputandlowlatency,complyingwiththeJESD238memorystandard.lt includesbothPHYandMemoryControllercomponentssupportingHBM3SDRAMspeedsrangingfrom 4.8Gbps/pinto6.4Gbps/pin.Flexibleconfigurationsareavailable,includingPHYOnly,PHY ^+ Controller, andControllerOnlytoaccommodate diversecustomerdesignspecifications.Additionally,thechip's footprintandpowerconsumptionarehighlycompetitivewithintheindustry.

OVERVIEW

TheDie-to-Dieinterfaceisafunctionalblockthatprovidesadatainterfacebetweentwochipdieswithin thesamepackageMSquaresD2DsolutioncompatiblewiththeUCle1.secificationincludesboth Die-to-Dieadapterlayerandaphysicallayer.Eachlayerfeaturesasidebandinterfacethatprovidesa back-channelforlinktrainingandaccesstotheregistersof thelinkpartnerasshowninFigure1.This uniquehybridanalog/digitalarchitectureofferslowpowerconsumptioncompactfootprintandrobust performancemakingitwell-suitedfortargetapplicationssuchashigh-performancecomputinglr multimediaSoCs,andDie-to-Dieinterconnections.

ONFI5.0IP

OVERVIEW

MSquareoffersa silicon-provenONFI5.0PHYIPthat supportsallmodesof theOpenNANDFlash Interface(ONFI)5.0 specification.ONFIis aninterface that connects external flash particles(NAND Flash)andinternalflashcontroller(NANDController),commonlyusedinSolidStateDrives(SSD）and embeddedmemory(eMMC)products.Tofacilitatecustomerimplementation,theMSquare'sONFI5.0 PHYsupportsexpandablechannelsandcustomizableCE/RBPadNumbers.

Figure 1:Architecture Diagram

Figure 2:BlockDiagram

MSquare'sONFI5.1PHYisahigh-performanceandlow-powerPHYIPwhichsupportsallmodesof the Open NAND Flash Interface(ONFI)5.1 specification.ONFI is an interface connecting external flash particles(NANDFlash）andinternalflashcontroller(NANDController),widelyusedinSolidStateDrive (SSD)productsosimlifytheimplementationMSquareONFI5.1PHYsupportsexpandablechannes andcustomizableCE/RBpadnumbers.

HIGHLIGHTS

Figure1:ArchitectureDiagram

MSquare'sLPDDR4XPHYisatransceiverphysical layerIPinterfacesolutiondesignedforASICsand SOCs.CompatiblewiththeuniversalIPprotocolDFI4.0itoperatesatadatarateofupto4267Mbpswith a16-bitdatawidthperchannel.AsdepictedinFigure1,theLPDDR4XPHYblockdiagramforsystem applicationincludesadataandaddresstransmitpathareceiverdatapath,aLLblockandmore. Featuringahybridanalog/digitlarchitcturequaredliverslwpowerconumptionom footprint,androbustperformance,makingitwell-suitedforPDDR4Xapplications.

HIGHLIGHTS

Figure 1:System-Level BlockDiagram

OVERVIEW

MSquare'sLPDDR5X/4XPHYisatransceiverphysicallayerIPinterfacesolutiondesigned forASICsand SOCs.CompatiblewiththeuniversalIPprotocolDFI5.0itoperatesatdataratesupto8533Mbpswitha 16-bit datawidthperchannel.Withflexible configurationoptions,theLPDDR5X/4XPHY supportsa varietyofmobileapplicationsusingPDDR5X,PDDR5andLPDDR4XDRAMs.Featuringahybrid analog/dgitlarchitctuequareliverswwrconsumtionmpactootritndrbu performance,makingitwell-suitedforLPDDR5X/4Xapplications.

HIGHLIGHTS

Figure 1:System-Level BlockDiagram

OVERVIEW

MSquaresDPHisahighlyreliablesolutionfordisplayintfacerequirmentsupportingresolutions of4KandhigherByperatingatubstantiallyhigherbitratesthisDPsoltionreducesboththenumer ofwiresandpinsrequiredomparedtointerfaceslieDVandMtisfullcomliantwith v1.5and1.4bstandards,andcapableofdrivingupto8.1Gb/speraneinconfigurationsupto4lanesl consistsofelectricalsub-blocksofmain-linkandAUXchannelofPHYforeDP.MSquareprovideseDPwith superiorPPAandofferscustomizationbasedoncustomerspecifications.

Figure 1:System-LevelBlock Diagram

PCle 4.0 IP

OVERVIEW

MSquareExpress4.Hnludeshigseedhighl-ficientandcost-ffctiveransiv to turbocharge today'shigh-performance and high-bandwidth aplications such as data centers, automotive,enterprisecomputing,andhigh-performanceembeddedsystems.

ThePCleIPboastsalowpowerconsumptionandcompactsiliconfootprint.ItsrobustPHYarchitecture tolerateprocessvoltageandtmerature)ariationshisPintgratesigh-speedmixedsia circuitsto supportPCle4.0 traffic at16Gbps.It isbackward compatiblewithPCle3.1datarates at 8.0Gbps,PCle2.1at5Gbps,andPCle1.1at2.5Gbps.hemulti-tabtransceiverdesign,accompand byarobustanmbddedbitrrorrateBstrandaninenaymonitrnaldig tocontroltest,andmonitorsignalintegritywithouttheneedforexpensivetestequipment.

HIGHLIGHTS

奎芯科技公众号

www.m2ipm2.com